Integrated circuits designed for data storage. These include volatile memory like RAM (working data storage) and non-volatile memory like flash and ROM (persistent storage).
15 articles
Memory makers big and small are innovating storage solutions to meet the mounting needs of AI, industrial factories, software-defined vehicles, and space exploration.
March 10, 2026– Joint R&D programs focused on advancing materials engineering and advanced packaging innovations for next-generation DRAM and high-bandwidth memory (HBM)– Opening this year, Applied’s EPIC Center is designed to provide chipmakers and ecosystem partners with earlier access to Applied’s R&D portfolio, faster cycles of learning and accelerated transfer...
Original Article By SemiVision Research [Reading time: 8 mins]
A new technical paper, “System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures,” was published by researchers at Georgia Tech. Abstract “3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery,...
The chiplets design combines IP access, interposer expertise, and relationships with HBM suppliers, foundries and OSATs worldwide. The post Scoping out the chiplet-based design flow appeared first on EDN.
Microns Result and The Rapid Transformation of the Semiconductor Memory Market
3D NAND subarray structures tilt during slit processing, demonstrating stress evolution, including deformation. The post Mechanical Stress in Semiconductor Development appeared first on IMAPS 3D InCites Content Platform.
Edge, in-sensor AI processors; TMDC-based transistors; DRAM read disturbance threshold; replay-based validation for chiplets; LLM-specific algorithmic attacks; noise in tellurium transistors; FMEDA safety metrics; HW reverse engineering; slowdowns in multi-GPU LLM inference. The post Chip Industry Technical Paper Roundup: Mar. 31 appeared first on Semiconductor Engineering.
Original Article By SemiVision Research [Reading time: 22 mins]
Why copper grain size matters for hybrid bonding and how to control it for HBM and chiplets. Read the article here. Abstract Hybrid bonding is reshaping advanced packaging by enabling ultra-fine pitch copper-to-copper interconnects, essential for high-bandwidth memory (HBM), chiplet integration, and 3D heterogeneous systems. While alignment precision, oxide control,...
Gigadevice doubled down on efficiency at Embedded World—unveiling a motor-control MCU that slashes system complexity and a low-voltage NOR flash that cuts power use by a third.
The undying thirst for smarter (historically, that means larger) AI models and greater adoption of the ones we already have has led to an explosion in data-center construction projects, unparalleled both in number and scale. Chief among them is Meta’s planned 5-gigawatt data center in Louisiana, called Hyperion, announced in...
How a next‑gen SRAM compiler IP for TSMC N5A and N3A helps design teams with measurable gains in PPA, reliability, and system robustness. The post Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs appeared first on Semiconductor Engineering.
A focus on DRAM and NAND is squeezing NOR wafer capacity and backend test resources. The post AI Demand Resets Memory Market Priorities, Tightening NOR Flash Availability appeared first on Semiconductor Engineering.
A new embedded memory architecture with a three-transistor cell. The post Reinventing Embedded Memory: Solving The SRAM Scaling Wall appeared first on Semiconductor Engineering.