The article discusses the importance of signal integrity in modern chip design, particularly focusing on clock integrity and clock jitter. These factors are critical for ensuring reliable performance in advanced semiconductor devices.
Researchers from KU Leuven and imec have published a paper discussing the challenges and considerations for introducing new extreme ultraviolet (EUV) resist materials into semiconductor fabs. The paper aims to guide both academia and entrepreneurs in navigating these complexities.
Intel's product marketing at CES has shown improvement in understanding market realities, although their AI marketing efforts fell short again. The PTL 18A process technology has been positively highlighted.
The article discusses a new lithography strategy that integrates a large exposure field with high-resolution imaging and algorithmic early zone correction. This approach aims to minimize alignment errors in the fabrication process of next-generation fan-out panel-level packaging (FOPLP).
The article discusses the significance of the 28nm process node in ASIC development, highlighting it as the last feasible node for many non-hyperscale teams. It emphasizes the economic and organizational shifts that occur when moving beyond this node.
The article discusses the complexities and cost sensitivities associated with the 40nm process node, which marks a significant shift from earlier nodes like 55nm. It highlights that first-time ASIC teams often face optimistic cost assumptions at this level due to increased risks and challenges.
The article discusses the unique characteristics of the 55nm process node, highlighting its differences from the 65nm node in terms of cost sensitivity and schedule risk. It also addresses the limitations of Multi-Project Wafer (MPW) services at this technology node.
The article clarifies that 90nm technology is often mischaracterized as merely a smaller version of 130nm, but it actually functions more like a transition node with significant cost sensitivity and design requirements. It discusses the costs associated with 90nm wafers and Multi-Project Wafer (MPW) services, highlighting when each option is appropriate.
The article discusses the 65nm process node as a critical transition point in custom silicon, where costs, complexity, and risks increase significantly. It highlights the common misconceptions teams have about cost assumptions at this node compared to older nodes.
The article discusses the evolving dynamics of wafer demand and node economics in the semiconductor industry, particularly as artificial intelligence (AI) influences the foundry landscape. It highlights the partnership between Apple and TSMC as a pivotal factor in shaping modern semiconductor manufacturing.
The article discusses the significance of the 130nm process node, which balances the benefits of mature analog processes and the need for higher density compared to 180nm. It also clarifies common misconceptions about the costs associated with Multi-Project Wafer (MPW) and full mask options at this node.
The 180nm process node continues to be a preferred choice for various semiconductor designs, particularly in analog and mixed-signal applications. Its cost-effectiveness is a significant factor influencing its ongoing popularity despite the emergence of more advanced nodes.
The article emphasizes that while booking a Multi-Project Wafer (MPW) shuttle is a common step towards silicon production, it does not guarantee a successful outcome if the design is not adequately prepared for tapeout. Many failures in MPW projects stem from unready designs rather than the choice of MPW itself.
The article discusses the common misconception that the most advanced semiconductor nodes yield the best products. It highlights that experienced teams often opt for the least aggressive node that still meets their product requirements to manage costs and risks effectively.
The article provides coverage of the International Electron Devices Meeting (IEDM), a key conference focused on advancements in semiconductor devices. It highlights the significance of the event as a platform for showcasing cutting-edge research and innovations in the industry.
Integrated circuit designers are finding that focused ion beam (FIB) techniques, traditionally used on older process nodes, are increasingly beneficial for advanced technology nodes like 28nm and beyond. This is particularly relevant as the cost to bring new devices to market continues to rise significantly.
The article lists the top ten semiconductor CEOs for 2025, highlighting industry leaders such as C C Wei, Jensen Huang, and Lisa Su. This recognition reflects their influence and contributions to the semiconductor landscape.
EMASS, a subsidiary of Nanoveu, is nearing the tape-out of its ECS-DoT SoC, which is built on a 16-nm process node. The project is progressing towards critical milestones including GDS sign-off and fabrication at TSMC.
Nvidia has decided not to proceed with Intel's 18A manufacturing process due to concerns over yield and performance. This decision follows Nvidia's $5 billion investment in Intel earlier in September.
The teardown of the Kirin 9030 chip reveals that SMIC's 'N+3' process has a lower transistor density compared to Samsung and TSMC's 5nm processes, despite aggressive scaling of metal pitch. This indicates potential challenges for SMIC in achieving competitive performance at advanced nodes.