The article explores the viability of Small Language Models (SLMs) in hardware design, particularly when integrated with an agentic AI framework. It highlights that SLMs can achieve near-large language model performance at a significantly lower cost through innovative workflows.
The article introduces FLEX, an FPGA-CPU accelerator designed to enhance mixed-cell-height legalization tasks by optimizing task assignments and employing multi-granularity pipelining techniques. Experimental results demonstrate significant speedups and improved legalization quality compared to existing solutions.
The article reviews the potential of resistive random-access memory (RRAM) for analog matrix computing in massive MIMO signal processing. It highlights recent advancements in using RRAM for tasks such as matrix-vector multiplication and MIMO detection, emphasizing its relevance in wireless communication.
The article discusses the challenges posed by data movement overhead in large-scale Mixture of Experts (MoE) Large Language Models (LLMs) and presents insights from profiling four state-of-the-art models. It highlights how understanding these patterns can lead to architectural improvements in wafer-scale GPUs for enhanced performance.
The paper introduces a new method for automated stripboard circuit layout design using Answer Set Programming (ASP), focusing on both synthesis and multi-objective optimization. It demonstrates the ability to create compact, manufacturable layouts while addressing complex design constraints effectively.
The article introduces ESACT, an end-to-end sparse accelerator designed to enhance the efficiency of compute-intensive Transformers by leveraging local similarity for sparse acceleration. This approach addresses the limitations of existing accelerators that primarily focus on intra-row sparsity and often incur high computational costs.
The paper introduces a method for enhancing the functional stability of neural networks by employing hardware redundancy at the neuron level. This approach allows the system to maintain operation despite individual hardware failures.
The article discusses a context-aware Mixture-of-Experts (MoE) system that utilizes CXL-enabled near-data processing (CXL-NDP) to optimize the inference of large language models. By dynamically managing expert placement and employing mixed-precision quantization, the system aims to reduce costly memory transfers and improve computational efficiency.
The article discusses a new method for accelerating the zero-means normalized cross correlation (ZNCC) algorithm on embedded GPUs, specifically targeting the Jetson Tx2. This approach aims to enhance processing speed while maintaining accuracy in mobile stereo-matching systems used in applications like automated driving and robotics.
The article introduces HLStrans, a benchmark-scale dataset designed for High-Level Synthesis (HLS) that includes over 124,000 paired C and HLS programs with testbenches. This dataset aims to facilitate the automation of hardware design transformations necessary for efficient FPGA implementations using large language models.
The article discusses a proposed custom-designed spatial array architecture aimed at enhancing wireless communication systems through reconfigurability and efficiency. This architecture is evaluated against specialized cores, highlighting its potential for diverse communications and sensing tasks.
The article introduces PRO-V-R1, an open-source framework designed to enhance Register-Transfer Level (RTL) verification, which currently consumes a significant portion of development time. It highlights the limitations of existing proprietary models and the need for a comprehensive solution in the verification space.
The article discusses the challenges of deploying large-scale Deep Learning models on edge devices due to computational and energy constraints. It introduces a hardware-aware Neural Architecture Search framework aimed at optimizing Early Exiting Neural Networks for edge accelerators, considering factors like quantization.
The article discusses the insights of Melanie Mitchell, a prominent computer scientist, on the current state of artificial intelligence and its implications. Her work has significantly shaped the understanding of AI's capabilities and limitations in recent years.
BYD has launched a revolutionary plug-in hybrid vehicle designed for the Brazilian market, capable of running on ethanol, gasoline, and electricity. This innovation marks a significant step in the evolution of flexible fuel vehicles, leveraging local biofuels.
The article discusses a method to use Large Language Models (LLMs) as lossless encoders and decoders to transform Logic Condition Tables (LCTs) into Hardware Description Language (HDL) code, addressing issues of hallucinations and omissions. This approach demonstrates significant productivity improvements in hardware logic design automation by accurately generating and reconstructing LCTs from HDL.
The paper addresses the complexities of detailed routing in semiconductor design, highlighting the inefficiencies of traditional pathfinding algorithms. It proposes using reinforcement learning to dynamically adjust routing cost weights, potentially reducing runtime and design rule violations.
The article introduces KVNAND, a novel architecture that enables large language model inference on edge devices without the need for DRAM by utilizing compute-enabled 3D NAND flash for both model weights and key-value cache. This innovation addresses the challenges of low arithmetic intensity and high bandwidth demands associated with traditional methods.
The article presents a lightweight unified hash engine that supports Sha-3 and Shake, designed with a fault-resilient mechanism to enhance reliability in post-quantum cryptography systems. It achieves significant improvements in area requirements and fault detection capabilities compared to existing solutions.
The article discusses Fletch, a framework for caching file-system metadata in programmable switches, addressing the challenges of cache consistency in distributed file systems. It highlights the importance of managing path dependencies specific to file-system semantics, which previous in-switch caching solutions have overlooked.