The article discusses the evolving role of GPUs in AI computation as the technology expands beyond traditional data centers. It highlights the increasing relevance of FPGAs in the AI data path due to system constraints.
Microchip Technology has enhanced its PolarFire FPGA ecosystem by introducing new SDI IP cores and a Quad CoaXPress Bridge Kit, aimed at developers requiring efficient video connectivity solutions. This expansion includes various tools and resources designed to facilitate development and improve security.
The article discusses the advantages of Siemens Veloce proFPGA CS for FPGA-based prototyping projects. It highlights how users can leverage this solution to enhance performance in their designs.
The article introduces RidgeWalker, a high-performance accelerator for Graph Random Walks (GRWs) on datacenter FPGAs, addressing challenges like data dependencies and irregular memory access. It highlights a novel asynchronous pipeline architecture that enables perfect pipelining and adaptive load balancing through a feedback-driven scheduler.
The article discusses the importance of selecting the right prototyping partner in the semiconductor industry, highlighting S2C's role in advanced FPGA-based SoC prototyping. The author expresses anticipation for an upcoming update from S2C at the DVCon event in March.
The paper introduces SparseLUT, a framework designed to optimize LUT-based deep neural networks for edge devices by addressing LUT size growth and connectivity issues. It achieves significant reductions in LUT consumption and inference latency while maintaining accuracy through architectural enhancements and a novel training algorithm.
The article discusses the increasing complexity of System-on-Chip (SoC) designs, which demand enhanced prototype capacity and efficiency. S2C aims to address these challenges with a high productivity toolchain for SoC bring-up.
Aldec, Inc. has launched ALINT-PRO™ 2025.12, which introduces new design rules aimed at enhancing mixed-language projects. This update is designed to improve correctness, maintainability, and interoperability of IP when using VHDL and other languages.
The Standardization Group for Embedded Technologies (SGET) has introduced the Open Harmonized FPGA Module (oHFM), marking a significant development in embedded design. This new specification is the first open and vendor-independent FPGA module standard, leveraging successful Computer-on-Module principles.
The paper presents a new methodology for selectively hardening RISCV soft processors on SRAM-based FPGAs by considering timing fragility. This approach enhances reliability while minimizing the overhead associated with full redundancy by focusing on routing-dependent timing sensitivity.
The article discusses a novel chunked FFT convolution method that allows for long-context reasoning on memory-constrained FPGAs, specifically the Alveo U200. This approach enables efficient processing of large sequences while maintaining performance despite limited Block RAM capacity.
The decision to build an ASIC is complex and often arises from various pressures such as rising FPGA costs and tightening power budgets. Teams may feel uneasy about remaining on their current platform while also fearing the risks associated with custom silicon development.
The article discusses the common misconception that transitioning to ASICs is always beneficial, highlighting that this assumption can lead to costly mistakes. It emphasizes that not all ASIC projects succeed, and failures often stem from overlooked factors rather than the technology itself.
The excerpt discusses how power issues in product design lead to unintended compromises that can degrade performance and functionality. It highlights the cumulative effect of these compromises on product efficiency over time.
The article discusses the complexity of determining the break-even point between ASIC and FPGA technologies, emphasizing that there is no one-size-fits-all answer. It suggests that teams often approach this question too late and with an oversimplified perspective.
The article introduces HFRWKV, an FPGA-based hardware accelerator designed to optimize the performance of the RWKV architecture, which faces challenges in GPU parallelism and memory bottlenecks. It highlights innovative strategies for hybrid-precision quantization and efficient computation methods to enhance performance while managing resource consumption.
The article discusses an automation framework for optimizing large language model (LLM) inference by utilizing weight pruning and low-bit quantization on FPGA platforms. It highlights a unified pipeline that enhances performance while reducing memory requirements across various hardware systems.
The article discusses the development of MERINDA, a hardware-accelerated framework for model recovery in physical AI applications at the edge. This framework aims to improve the efficiency of learning and inference for autonomous systems operating under strict resource constraints.
The article introduces HLS4PC, a parameterizable HLS framework designed for FPGA acceleration of 3D point cloud models, which are typically resource-intensive when run on GPUs. It highlights the framework's ability to optimize performance through hardware-aware compression techniques, resulting in a significantly less complex model with minimal accuracy loss.
The article discusses ADAPTOR, a runtime-adaptive accelerator designed for transformer neural networks on FPGAs, which addresses the high computational and memory demands of these models. It highlights the challenges of designing custom accelerators and the need for adaptability in processing transformer models efficiently.