FPGA

The article introduces FLEX, an FPGA-CPU accelerator designed to enhance mixed-cell-height legalization tasks by optimizing task assignments and employing multi-granularity pipelining techniques. Experimental results demonstrate significant speedups and improved legalization quality compared to existing solutions.

ArXiv Hardware

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis

Dec 04, 2025

The article introduces HLStrans, a benchmark-scale dataset designed for High-Level Synthesis (HLS) that includes over 124,000 paired C and HLS programs with testbenches. This dataset aims to facilitate the automation of hardware design transformations necessary for efficient FPGA implementations using large language models.

ArXiv Hardware

The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates

Dec 03, 2025

The BrainScaleS-2 SoC combines analog neuron and synapse circuits with digital components, including CPUs and FPGA connectivity, to enhance neuromorphic computing. It achieves low chip-to-chip latencies through a sophisticated interconnection system, enabling efficient data processing in a compact rack format.

EE Journal

Time to first prototype shouldn’t be so hard! — Siemens

Dec 03, 2025

The article discusses the challenges associated with FPGA-based prototyping and highlights how Siemens' VPS platform can simplify the process. It emphasizes features like automatic partitioning and debug infrastructure to enhance project efficiency.

EE Times

Efinix Redefines the Future of Programmable Hardware and Edge AI

Dec 03, 2025

Efinix is a Silicon Valley startup that is transforming programmable hardware and edge AI with its innovative FPGA technology. The article highlights the company's journey and its potential impact on the industry.

ArXiv Hardware

Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs

Dec 01, 2025

The article discusses the challenges of timing optimization in global placement for large-scale heterogeneous FPGAs, particularly due to complex interconnects and nonlinear constraints. It introduces TD-Placer, a new framework that utilizes graph-based representations and nonlinear models to enhance timing accuracy and overall placement quality.

Embedded.com

Infineon HYPERRAM Validated for AMD FPGA platform

Dec 01, 2025

Infineon Technologies AG's 64-Mb HYPERRAM device has been validated for use with AMD's Spartan UltraScale+ FPGA SCU35 evaluation kit. This integration allows the AMD MicroBlaze V soft-core RISC-V processor to utilize a high-bandwidth external memory subsystem cost-effectively.

ArXiv Hardware

Design and Implementation of a Takum Arithmetic Hardware Codec

Nov 26, 2025

The article discusses the design and implementation of a hardware codec for the takum arithmetic format, which offers enhancements over the posit number format. This codec, implemented in VHDL, showcases improved precision and dynamic range, particularly for small and large magnitude numbers.

ArXiv Hardware

Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration

Nov 26, 2025

The article introduces Bombyx, a compiler toolchain that translates OpenCilk programs into a format suitable for FPGA hardware acceleration. It emphasizes a shift from OpenCilk's implicit task model to a more efficient explicit continuation-passing model, aligning better with FPGA architectures.

ArXiv Hardware

Scalable FPGA Framework for Real-Time Denoising in High-Throughput Imaging: A DRAM-Optimized Pipeline using High-Level Synthesis

Nov 25, 2025

The article presents a scalable FPGA-based preprocessing pipeline designed for real-time denoising in high-throughput imaging workflows. This architecture, optimized for DRAM-backed buffering, enhances processing capabilities by minimizing latency and enabling inline denoising.

EE Times

Mastiska Raises $10M Seed For Sovereign AI Chip Play in UAE

Nov 25, 2025

Mastiska, a UAE-based startup, has secured $10 million in seed funding to develop an FPGA-based data center product. This initiative aims to create sovereign AI chips in the UAE.

EE Journal

AMD successfully tests Infineon’s HYPERRAM™ memory and IP on the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit

Nov 25, 2025

Infineon Technologies announced that AMD has successfully tested its HYPERRAM™ memory and controller IP on the Spartan UltraScale+ FPGA SCU35 Evaluation Kit. This integration supports the AMD MicroBlaze V soft-core RISC-V processor, providing a cost-effective and high-bandwidth memory solution.

Semiconductor Engineering

FPGAs Find New Workloads In The High-Speed AI Era

Nov 25, 2025

The article discusses the expanding applications of FPGAs in various sectors, particularly in life science AI and wireless networking. These advancements aim to alleviate memory and I/O bottlenecks while adapting to evolving protocols.

EE Times

Smarter Silicon with Menta eFPGA and HW/SW Co-Design

Nov 24, 2025

Menta's eFPGA and HW/SW Co-Design are set to deliver significant performance enhancements and flexibility in modern ASICs and SoCs. These advancements promise to improve crypto-agility, making them more adaptable to evolving security needs.

r/FPGA

Opinions on Defense Industry?

Nov 20, 2025

A new graduate is weighing two job offers: one from a tech company and another from a defense contractor for an FPGA/Digital Design engineer role. They seek insights on the defense industry, particularly regarding work pace, technology, and work-life balance.

r/FPGA

Would you recommend a masters?

Nov 20, 2025

A senior in computer engineering is struggling to find entry-level FPGA roles and is considering pursuing a master's degree as a backup plan. They are seeking advice on whether a master's is worthwhile and what specific programs might be beneficial.

r/chipdesign

How relevant is an FPGA internship for chip design?

Nov 20, 2025

A junior Computer Engineering student is excited about an upcoming FPGA and VHDL-focused internship at a defense company but seeks clarity on how this experience relates to future chip design roles. They are looking for advice on skills to prioritize during the internship to aid their long-term career in chip design.

r/FPGA

Recent grad that’s looking around in the market

Nov 20, 2025

A recent graduate from Sydney is seeking job opportunities related to FPGAs and has some relevant experience through personal projects and a thesis. The individual is reaching out for advice and potential job leads from the community.

r/FPGA

Can we program Upduino using Vivado?

Nov 20, 2025

The author seeks guidance on programming the UPduino board using Vivado after having experience with Zedboard. They prefer an IDE environment over command-line tools and are looking for resources to facilitate their programming efforts.

r/FPGA

Student aiming for FPGA: is this learning curve actually worth it?

Nov 20, 2025

A college student expresses frustration with the steep learning curve associated with FPGA development, highlighting challenges with tools like Vivado and Quartus. The student is concerned about skill development and internship preparation amidst a lack of structured learning.

Browse

Hot Topics

FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis

The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates

Time to first prototype shouldn’t be so hard! — Siemens

Efinix Redefines the Future of Programmable Hardware and Edge AI

Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs

Infineon HYPERRAM Validated for AMD FPGA platform

Design and Implementation of a Takum Arithmetic Hardware Codec

Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration

Scalable FPGA Framework for Real-Time Denoising in High-Throughput Imaging: A DRAM-Optimized Pipeline using High-Level Synthesis

Mastiska Raises $10M Seed For Sovereign AI Chip Play in UAE

AMD successfully tests Infineon’s HYPERRAM™ memory and IP on the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit

FPGAs Find New Workloads In The High-Speed AI Era

Smarter Silicon with Menta eFPGA and HW/SW Co-Design

Opinions on Defense Industry?

Would you recommend a masters?

How relevant is an FPGA internship for chip design?

Recent grad that’s looking around in the market

Can we program Upduino using Vivado?

Student aiming for FPGA: is this learning curve actually worth it?