Samsung plans to increase its DRAM production by only 5% to 4 million wafers this year, according to reports from DigiTimes. This modest growth contrasts with broader expectations for the DRAM industry to expand production significantly.
The article discusses how a new storage tier can enhance long context inference for AI agents while significantly reducing cache storage costs. It also highlights the specifics of the storage system, potential market leaders, and associated risks.
The Mostek MK4116 and MK4164 DRAM chips were pivotal in shaping the microcomputer landscape of the late 1970s and early 1980s. Their introduction established industry standards that influenced subsequent DRAM designs.
The article discusses the increasing importance of GDDR7 memory in enhancing memory throughput and efficiency for AI inference applications. It highlights a shift in focus from solely raw compute power to the overall performance of memory systems.
The adoption of hybrid bonding in HBM4 has been delayed due to process cost and yield issues, leading to a continued reliance on microbumps. This decision reflects ongoing challenges in advancing packaging technologies within the semiconductor industry.
The DRAM industry is entering 2026 following a tumultuous year characterized by significant fluctuations. This sets the stage for new developments influenced by advancements in AI technology.
Surging memory prices are negatively impacting notebook brands by squeezing their profit margins and limiting their pricing flexibility. As a result, global notebook shipments are projected to decline by 5.4% year-over-year in 2026, reaching 173 million units.
The article discusses various advancements in semiconductor technology, including improvements in DDR5 memory and innovative techniques for chip integration and design. It highlights research on hybrid bonding, radiation effects, and new memory technologies like 2T-SOT-MRAM.
Georgia Tech's new paper explores the effects of DRAM writes on DDR5-based systems, emphasizing the importance of buffering write requests to optimize performance. The study introduces a method called BARD, which aims to reduce write latency by leveraging bank-parallelism.
The article discusses how the increasing demand for AI technologies is outpacing the supply of DRAM, leading to shortages and rising prices. This trend highlights the critical role of DRAM in supporting AI applications.
The paper explores how write operations in DDR5 memory can significantly affect system performance due to varying latencies based on bank access patterns. By optimizing the write stream to prioritize lower-latency operations, performance can be improved despite the current limitations imposed by cache replacement policies.
The paper introduces PIM-FW, a hardware-software co-design aimed at optimizing the all-pairs shortest paths (APSP) algorithm using processing in and near memory architecture. This approach seeks to enhance performance by leveraging specialized parallel processing elements and a novel dataflow for improved load balancing.
The article discusses the increasing steepness of the HBM (High Bandwidth Memory) supply curve, indicating a growing gap between supply and demand. Despite this steepening, the supply still fails to meet the rising demand in the market.
The article introduces DreamRAM, a modeling tool designed for custom 3D die-stacked DRAM, which allows for fine-grained configuration of bandwidth, capacity, energy, latency, and area. This tool aims to address the diverse demands of various applications in high-performance computing, graphics, and machine learning.
The article introduces RACAM, a novel in-DRAM Processing-In-Memory architecture designed to enhance efficiency for memory-intensive tasks, particularly in machine learning inference. It addresses significant limitations in existing systems by enabling data reuse and optimizing workload mapping.
The article discusses the importance of measuring and monitoring gate profiles, film thickness, and structural uniformity at the nanometer scale in semiconductor manufacturing. It highlights the role of Optical Critical Dimension (OCD) in the context of Gate-All-Around (GAA) logic and vertical gate DRAM process control.
Micron has announced its exit from the Crucial consumer DRAM business, ceasing sales of its consumer-branded products globally. This decision reflects a strategic shift in response to market conditions affecting the DRAM segment.
The global DRAM industry experienced a significant revenue increase of 30.9% quarter-over-quarter, reaching $41.4 billion in Q3 2025. This growth was driven by rising conventional DRAM contract prices, increased bit shipments, and higher volumes of high-bandwidth memory (HBM).
The article presents a scalable FPGA-based preprocessing pipeline designed for real-time denoising in high-throughput imaging workflows. This architecture, optimized for DRAM-backed buffering, enhances processing capabilities by minimizing latency and enabling inline denoising.
Framework has halted the sale of standalone RAM to combat scalpers, leaving limited DDR4 options available for purchase. The company plans to bundle remaining DDR5 inventory with its DIY Edition laptops as it anticipates rising memory prices due to increased demand from AI applications.