The article discusses the rising importance of power delivery in semiconductor design, particularly in the context of AI applications. It highlights new power-delivery chiplets that could potentially reduce AI power consumption by 50%.
The article discusses various technical advancements in the semiconductor industry, including developments in 3D interconnected networks, neuromorphic accelerators, and memristor-based devices. It highlights the importance of open-source chiplets for high-performance computing and artificial intelligence applications.
The article discusses the growing interest in glass interposer substrates and hybrid bonding techniques in semiconductor packaging. It highlights a recent publication that explores these technologies in detail, authored by industry experts.
The article discusses the importance of validating design kits for chiplets, emphasizing the need for investment and collaboration throughout the supply chain. This approach can lead to fewer layout respins and reduced risk in chip design.
The article presents a chiplet-based RISC-V SoC architecture designed to enhance performance and efficiency for edge AI devices. It introduces four key innovations aimed at overcoming the limitations of traditional monolithic SoC designs.
The article discusses how advancements in packaging technologies can enhance the interconnection resources for chiplets, facilitating the development of larger and more energy-efficient VLSI systems. It highlights the potential to simplify ESD protection and signaling, which could lead to smaller chiplet sizes.
Researchers from Arizona State University and the University of Minnesota have published a paper discussing advancements in ESD protection and signal integrity for 2.5D/3D packaging technologies. The paper highlights how scaling these advanced packaging technologies can enhance interconnection resources for heterogeneous integration in VLSI systems.
Researchers from ETH Zurich and the University of Bologna have published a roadmap for open-source chiplet-based RISC-V systems aimed at high-performance computing (HPC) and artificial intelligence (AI). The initiative seeks to bridge the performance gap with proprietary designs, starting with a project named Occamy.
Brewer Science will co-present technical papers with imec at EPTC 2025, focusing on advancements in thin interposer assembly and flash-lamp debonding. These contributions aim to enhance reliable die-to-wafer integration, building on previous developments in hybrid bonding and laser debonding.
An industry-wide survey involving over 900 professionals has been conducted to assess the current state of intellectual property (IP) and design data management in the semiconductor sector. The findings aim to highlight challenges, solutions, and best practices in this critical area.
Applied Materials and BESI have introduced the Kinex hybrid bonding system aimed at enhancing advanced chiplet packaging. This development marks a significant step towards high-volume manufacturing in the semiconductor sector.
The article discusses how evolving standards and design-for-test strategies are enhancing production testing for advanced chiplet architectures, specifically 2.5D and 3D designs. It emphasizes the role of automation in improving efficiency in semiconductor packaging.
A new pilot line is being established to optimize the production process for large organic interposers. This initiative aims to enhance volume production capabilities in the semiconductor sector.
The article discusses Arm's recent announcement regarding its Chiplet Ecosystem, highlighting the potential for modular chip design. This initiative aims to enhance flexibility and performance in semiconductor manufacturing.
The article discusses the alignment of Arm’s CSA, Neoverse CSS, and Total Design frameworks to establish a multi-vendor chiplet ecosystem. This collaboration aims to enhance interoperability and design efficiency among chiplet manufacturers.
The article discusses Eliyan, a new chiplet interconnect technology supported by major HBM manufacturers and foundries, developed by experts in networking. This innovation aims to enhance chiplet integration and performance in semiconductor designs.