The article emphasizes the importance of detailed agreement between customers and ASIC developers on design specifications. This collaboration is crucial for successful ASIC development.
The interview with Jens Milnikel highlights the innovative technologies and strategic vision of ams OSRAM's CMOS Sensors ASICs division. It emphasizes the importance of human stories and partnerships in establishing the company as a leader in sensing solutions.
The article discusses the historical significance of Moore's Law in guiding semiconductor technology development over the past fifty years. It suggests that the industry is now evolving beyond this principle as new paradigms emerge in embedded computing.
The article introduces the XgenSilicon ML Compiler, which automates the transformation of machine learning models into optimized RISC-V assembly code for ASIC accelerators. It highlights five innovations that enhance Power, Performance, and Area (PPA) metrics over conventional methods.
The article introduces Platinum, a lightweight ASIC accelerator designed for efficient low-bit weight matrix multiplication, particularly for large language models. It addresses existing limitations in LUT-based methods by reducing overhead and enabling adaptive path switching for improved performance.
The Immutable Tensor Architecture (ITA) proposes a novel approach to AI inference by treating model weights as physical circuit topology rather than mutable software data. This shift aims to eliminate the memory hierarchy, significantly reducing energy costs associated with fetching model weights from DRAM.
The article introduces a 0.32 mm² ASIC designed for SIMO receivers that integrates jammer mitigation, channel estimation, and data detection using the MAED algorithm. This design, fabricated in 22 nm FD-SOI, achieves a throughput of 100 Mb/s at 223 mW, significantly outperforming existing solutions in terms of efficiency and performance.
The article introduces a new ASIC designed for jammer-resilient multi-antenna time synchronization, capable of supporting synchronization between a single-antenna transmitter and a 16-antenna receiver. This 65 nm ASIC features a core area of 2.87 mm², consumes 310 mW, and operates at a sampling rate of 1.28 MS/s.
The article discusses the evolution of Large Language Models (LLMs) and the need for advanced inference pipelines that incorporate multi-stage processes. It introduces HERMES, a simulator designed to model these complex workflows across diverse hardware architectures.
Menta's eFPGA and HW/SW Co-Design are set to deliver significant performance enhancements and flexibility in modern ASICs and SoCs. These advancements promise to improve crypto-agility, making them more adaptable to evolving security needs.
GUC and VSORA have collaborated to provide turnkey ASIC design services for the Jotunn8 datacenter AI inference processor. This partnership aims to ensure the successful tapeout of the new processor.
A solo miner has successfully mined a full Bitcoin block using a low-powered ASIC with just 6 terahashes per second, achieving this feat against odds of approximately one in 180 million. This event highlights the potential for individual miners to compete in a landscape dominated by larger mining operations.
The article reflects on a prediction made by Nathan Myhrvold, Microsoft’s CTO, regarding the future of computing, drawing a parallel between the intelligence of computers and that of his dog. It highlights a nostalgic look at the evolution of technology over the past 28 years.
A final year Electronics and Communication Engineering student is seeking job and internship opportunities in Digital VLSI, highlighting their proficiency in EDA tools and hands-on experience with Edge AI SoCs. They have also worked on various architectures and low-power design techniques.
A junior Computer Engineering student is excited about an upcoming FPGA and VHDL-focused internship at a defense company but seeks clarity on how this experience relates to future chip design roles. They are looking for advice on skills to prioritize during the internship to aid their long-term career in chip design.
The user seeks guidance on building the RISC-V Vector Extension from scratch using Verilog and plans for ASIC implementation, focusing on basic instructions. They are utilizing Cadence tools and have some foundational knowledge of the base ISA and vector registers.
The article discusses the emergence of analog neuromorphic processors designed for ASICs and SoCs, which enable low-power edge AI applications. This innovation is likened to the early days of microprocessors, emphasizing the transformative potential of these technologies in real-world applications.
The author reflects on their first experience with the RTL-to-gates flow in digital design, highlighting the complexity of synthesizing Verilog and managing timing constraints. They seek advice on how to deepen their understanding of key concepts like standard-cell libraries and synthesis reports.
A recent graduate has received an offer from a defense contractor for embedded work and FPGA development while also considering pursuing a master's degree in hardware accelerator design. They seek advice on balancing industry experience with academic research to achieve their career goals of working for top-tier companies like NVIDIA or AMD.
Triple-1 has introduced the Kamikaze III, a 3-nm ASIC chip designed for Bitcoin mining that achieves an impressive efficiency of 10.45 J/TH. This advancement highlights the ongoing innovation in cryptocurrency mining technology.