Aldec, Inc. has launched ALINT-PRO™ 2025.12, which introduces new design rules aimed at enhancing mixed-language projects. This update is designed to improve correctness, maintainability, and interoperability of IP when using VHDL and other languages.
Bio-RV is a low-power RISC-V processor designed for biomedical applications, featuring a compact architecture suitable for implantable devices. It operates at 50 MHz and is optimized for resource efficiency, making it ideal for various biomedical control tasks.
The article discusses the development of a new tool designed to find lightweight implementations of quadratic vectorial Boolean functions, particularly for cryptographic applications. It highlights the limitations of existing synthesis tools that focus on larger functions, emphasizing the need for dedicated solutions for smaller functions.
The article discusses the significance of the 28nm process node in ASIC development, highlighting it as the last feasible node for many non-hyperscale teams. It emphasizes the economic and organizational shifts that occur when moving beyond this node.
The article discusses the complexities and cost sensitivities associated with the 40nm process node, which marks a significant shift from earlier nodes like 55nm. It highlights that first-time ASIC teams often face optimistic cost assumptions at this level due to increased risks and challenges.
The article discusses the 65nm process node as a critical transition point in custom silicon, where costs, complexity, and risks increase significantly. It highlights the common misconceptions teams have about cost assumptions at this node compared to older nodes.
The article discusses the complexities of determining ASIC feasibility, emphasizing that it is not a straightforward yes/no decision. It highlights the need to balance economics, risk, schedule, and technical realities in ASIC projects.
The article discusses a decision-making tool for determining whether to use ASICs (Application-Specific Integrated Circuits) in semiconductor designs. This tool aims to streamline the design process by providing insights into the benefits and drawbacks of ASIC implementation.
The decision to build an ASIC is complex and often arises from various pressures such as rising FPGA costs and tightening power budgets. Teams may feel uneasy about remaining on their current platform while also fearing the risks associated with custom silicon development.
The article discusses the outdated perception that ASICs are only for large companies with significant budgets, highlighting that startups often misjudge the timing for ASIC adoption. It warns against both delaying the consideration of ASICs and rushing into them prematurely.
The article discusses the common misconception that transitioning to ASICs is always beneficial, highlighting that this assumption can lead to costly mistakes. It emphasizes that not all ASIC projects succeed, and failures often stem from overlooked factors rather than the technology itself.
The article discusses how teams often overlook the rising costs of their Bill of Materials (BOM) until it becomes a significant business constraint. As production scales, the initial flexibility in margins diminishes, leading to increased pressure on procurement and engineering teams.
The excerpt discusses how power issues in product design lead to unintended compromises that can degrade performance and functionality. It highlights the cumulative effect of these compromises on product efficiency over time.
The excerpt discusses the transition from Multi-Project Wafer (MPW) success to the production phase in ASIC development. It highlights that while achieving first silicon is a significant milestone, it marks the beginning of a new set of challenges rather than the end of the journey.
The article discusses the challenges faced during the ASIC quoting process, highlighting issues such as wide cost ranges and lengthy timelines. It suggests that the root of these problems often lies in the inadequacy of the Request for Quotation (RFQ) provided by clients.
The article discusses that most ASIC project failures are not due to poor ideas but rather due to misunderstood or postponed risks. By the time these risks become apparent, the projects are often too costly and complex to halt or rectify.
The article discusses the common misconception that the most advanced semiconductor nodes yield the best products. It highlights that experienced teams often opt for the least aggressive node that still meets their product requirements to manage costs and risks effectively.
First-time ASIC conversations often fail due to misaligned expectations between teams and vendors. This misalignment can lead to frustration, slow quotes, and missed schedules.
The article discusses the complexity of determining the break-even point between ASIC and FPGA technologies, emphasizing that there is no one-size-fits-all answer. It suggests that teams often approach this question too late and with an oversimplified perspective.
The article discusses how most ASIC development schedules fail due to unrealistic expectations about the linearity of progress and the ease of making changes. It emphasizes that ASIC development is heavily influenced by physical constraints and verification complexities, leading to costly late changes.