Curtiss-Wright and Green Hills Software have developed a COTS processing module utilizing the 13th Gen Intel Core i7 processor, aimed at enhancing safety-critical avionics systems. This module, named the V3-1222, is designed to make safety-certifiable computing more accessible.
OpenACM is introduced as the first open-source compiler designed for SRAM-based approximate Digital Compute-in-Memory (DCiM) architectures, addressing the challenges posed by the memory wall in data-intensive AI workloads. It enables designers to optimize energy consumption through accuracy-configurable multipliers, facilitating fine-grained accuracy-energy trade-offs.
The paper introduces Value Level Parallelism (VLP) as a method to enhance the efficiency of large language models (LLMs) by improving general matrix multiply operations. It also presents a new architecture, Mugi, which incorporates these innovations to optimize LLM performance and accuracy.
The article argues that the era of traditional software development, akin to PDFs, is being replaced by more flexible and efficient methods, represented by markdown. It suggests that memory hierarchies serve as a better analogy for the evolution of software, indicating a shift in value creation within the industry.
SiFive is set to integrate Nvidia's NVLink Fusion into its datacentre-class designs, enhancing the capabilities for AI systems based on RISC-V architecture. This integration will combine advanced processing cores with scalable coherent fabrics.
The article discusses the unique challenges of Large Language Model (LLM) inference, particularly focusing on memory and interconnect issues rather than compute power. It proposes four architectural research opportunities to enhance memory capacity and communication speed in datacenter AI applications.
The paper addresses the increasing complexity of workloads in extended reality (XR) applications, which require ultra-low-latency performance while managing power and area constraints. It proposes a cross-layer architectural classification to better understand and optimize these diverse workloads beyond traditional CNN-centric approaches.
The article discusses FaTRQ, a new system designed to enhance Approximate Nearest-Neighbor Search (ANNS) by eliminating the need to fetch full-precision vectors from slower storage. It introduces a tiered memory approach that utilizes compact residuals for faster refinement of candidate scores.
Synopsys has divested its Processor IP Solutions business to GlobalFoundries, following its acquisition of MIPS which included RISC-V IP software and tools. The financial details of the transaction remain undisclosed.
The article discusses how the integration of previously isolated components in modern system design is leading to the breakdown of traditional design abstractions. This shift necessitates a reevaluation of verification processes, positioning them as a critical discipline throughout the product lifecycle.
The article discusses advancements in garbage collector scanning for .NET CoreCLR, specifically targeting Arm64 architecture. These improvements aim to enhance runtime performance for applications that require significant memory resources.
The article discusses the importance of optimizing Neural Processing Units (NPUs) due to tight Power, Performance, and Area (PPA) constraints and the need for accurate workload representation. These factors are critical for enhancing the efficiency and effectiveness of NPUs in various applications.
Innatera is collaborating with a VLSI expert to provide training for engineers in neuromorphic computing. This initiative aims to enhance accessibility to next-generation AI hardware.
The article discusses the growing interest in Processing in Memory (PIM) technologies, which have been around for over 60 years. It aims to provide an annotated bibliography to support a forthcoming article on the subject.
GlobalFoundries' MIPS is set to acquire the ARC IP business from Synopsys as Synopsys refocuses on its core IP operations. This acquisition aligns with GlobalFoundries' strategy to enhance its capabilities in physical AI.
The article discusses the critical role of quantum error correction (QEC) in enabling production-level quantum computing, highlighting its necessity due to the rapid accumulation of errors in quantum systems. It draws a parallel between QEC and classical error correction methods, emphasizing the urgency for effective QEC solutions.
Quilter has successfully utilized AI to design a fully functional Unix computer, significantly reducing the typical PCB design timeline from a quarter to just one week. This breakthrough demonstrates the potential of AI in accelerating hardware development processes.
The article discusses the importance of ensuring timely data delivery to shared memory in semiconductor chips. This challenge is critical for optimizing performance and efficiency in chip design.
The article discusses the advantages of PCIe switches, particularly their ability to increase accessibility to more endpoints and facilitate data center disaggregation. Experts Lou Ternullo from Rambus and Wesley Yung from Astera Labs share insights on the technology's applications in a video from PCI-SIG.
The blog post discusses various topics including LLVM sanitizers, LLM inference acceleration, and the integration of software and automation. It also touches on issues like screen stuttering and sustainability in the semiconductor industry.