The article provides a roundup of significant developments in edge AI, quantum chips, and embedded computing, highlighting the release of the ESD November 2025 eBook. It encourages readers to explore additional resources on the Embedded website for more insights.
Qilimanjaro CEO Marta Estarellas discusses the current surge in quantum computing and its potential future developments. The article highlights the competitive landscape as companies seek to identify the next major player in this emerging field, akin to Nvidia's impact on GPUs.
The article highlights the most viewed stories on Electronics Weekly, including Nvidia's investment in Synopsys, Marvell's acquisition of a photonics startup, and Samsung's launch of a tri-fold phone. These developments reflect significant trends in the semiconductor and technology sectors.
IBM CEO Arvind Krishna expresses concerns that current investments in datacenters for AI development are unlikely to yield profitable returns. This statement highlights the financial challenges associated with scaling AI infrastructure.
Melexis has developed a new algorithm for people detection, counting, and localization using its MLX90642 far-infrared thermal array. This solution offers a privacy-preserving alternative for monitoring people in various environments.
The article explores the viability of Small Language Models (SLMs) in hardware design, particularly when integrated with an agentic AI framework. It highlights that SLMs can achieve near-large language model performance at a significantly lower cost through innovative workflows.
The article reviews the potential of resistive random-access memory (RRAM) for analog matrix computing in massive MIMO signal processing. It highlights recent advancements in using RRAM for tasks such as matrix-vector multiplication and MIMO detection, emphasizing its relevance in wireless communication.
The article discusses the challenges posed by data movement overhead in large-scale Mixture of Experts (MoE) Large Language Models (LLMs) and presents insights from profiling four state-of-the-art models. It highlights how understanding these patterns can lead to architectural improvements in wafer-scale GPUs for enhanced performance.
The article introduces ESACT, an end-to-end sparse accelerator designed to enhance the efficiency of compute-intensive Transformers by leveraging local similarity for sparse acceleration. This approach addresses the limitations of existing accelerators that primarily focus on intra-row sparsity and often incur high computational costs.
The paper introduces a method for enhancing the functional stability of neural networks by employing hardware redundancy at the neuron level. This approach allows the system to maintain operation despite individual hardware failures.
The article discusses a context-aware Mixture-of-Experts (MoE) system that utilizes CXL-enabled near-data processing (CXL-NDP) to optimize the inference of large language models. By dynamically managing expert placement and employing mixed-precision quantization, the system aims to reduce costly memory transfers and improve computational efficiency.
The article discusses a new method for accelerating the zero-means normalized cross correlation (ZNCC) algorithm on embedded GPUs, specifically targeting the Jetson Tx2. This approach aims to enhance processing speed while maintaining accuracy in mobile stereo-matching systems used in applications like automated driving and robotics.
The article introduces HLStrans, a benchmark-scale dataset designed for High-Level Synthesis (HLS) that includes over 124,000 paired C and HLS programs with testbenches. This dataset aims to facilitate the automation of hardware design transformations necessary for efficient FPGA implementations using large language models.
The article introduces PRO-V-R1, an open-source framework designed to enhance Register-Transfer Level (RTL) verification, which currently consumes a significant portion of development time. It highlights the limitations of existing proprietary models and the need for a comprehensive solution in the verification space.
The article discusses the challenges of deploying large-scale Deep Learning models on edge devices due to computational and energy constraints. It introduces a hardware-aware Neural Architecture Search framework aimed at optimizing Early Exiting Neural Networks for edge accelerators, considering factors like quantization.
Researchers from the University of Osaka and other institutions have published a paper on a new method for gate-tunable ionothermoelectric cooling in solid-state nanopores. This research addresses the critical challenge of efficient heat dissipation at the nanoscale in high-performance microelectronics.
Microsoft has lowered its sales expectations for its AI products, indicating potential challenges in the market. Additionally, Snowflake's performance raises concerns about the broader AI sector's health.
The article discusses the insights of Melanie Mitchell, a prominent computer scientist, on the current state of artificial intelligence and its implications. Her work has significantly shaped the understanding of AI's capabilities and limitations in recent years.
The article discusses AWS's new Trainium3 architecture, which features significant software and system enhancements aimed at optimizing performance per total cost of ownership. It also highlights the introduction of the 'Amazon Basics' GB200 NVL36x2 and collaborations with Astera Labs for further advancements.
The article discusses a webinar on Defacto's SoC Compiler AI, which aims to simplify the complex process of System-on-Chip design by utilizing human language. This innovation addresses the challenges posed by intricate EDA tool flows that often lead to significant time losses in configuration.